In multi-level cell (MLC) flash memories, least significant bit (LSB) and most significant bit (MSB) pages are encoded and written independently in order to maintain high write/read throughputs. This is done despite an evident correlation in the error mechanisms of LSB and MSB pages on the same physical wordline. Joint encoding/decoding of the LSB/MSB pages allows operating at an endurance beyond the rated endurance of the flash data block, but is not utilized because write/read throughput is more important. To reduce cell-to-cell interference and write latency a two-step programming process is employed for writing of the LSB and MSB pages on the same wordline. This process works to reduce the programming voltage swings between the original and target gray-coded cell states, and since large voltage swings results in more neighborhood cell voltage disturbance, less interference to those neighboring cells is caused by programming the current page. In addition, larger voltage swings mean more write delay as the latency of a incremental step pulse programming (ISPP) process is linearly proportional to the desired voltage swing. Hence, a double tiered programming process is employed, where the LSB is programmed by wider voltage increments, which results in a rough middle state distribution. At some point afterwards, when the MSB page is to be written, the LSB page is read from flash without passing through ECC, and finally both pages are written with a finer step pulse, which results in precise final state distribution. This approach can optimize write throughput on average, but a disadvantage is the possibility of misplacing the final state due to errors in reading the LSB page.
It would be desirable to have a method and/or apparatus for mitigating write errors in multi-level cell (MLC) flash memory through adaptive error correction code (ECC) decoding.